1. Field of the Invention
The present invention relates to an analog-to-digital converter having a digital correcting function and a wireless receiver including the analog-to-digital converter.
2. Background Art
In the field of next-generation industrial altimeter measurement such as a semiconductor inspecting device and a semiconductor manufacturing device and in the field of next-generation wireless communication system such as software radio and cognitive radio, an analog-to-digital converter having a high effective resolution of 10 bits or more and an extremely high conversion rate of 1 GS/s or more is required.
To provide such an ultrafast and high-resolution analog-to-digital converter, various unfavorable characteristics of an analog circuit constituting the analog-to-digital converter need to be digitally corrected. Various techniques of correcting gain shortage of an amplifier in an analog circuit (Non-patent Documents 1 and 2) and various techniques of correcting the influence of skew that is a static time deviation of a sampling timing of an analog-to-digital converter (Non-patent Documents 3 and 4) are conventionally suggested.
However, it is difficult to correct the influence of a jitter that is a random time deviation of a sampling timing by performing adaptive control using a least mean square (LMS) algorithm because of its random properties. For example, to provide an effective resolution of 10 bits or more at a conversion rate of 1 GS/s, it is required that a jitter of a sampling clock is approximately 1 ps rms or less. Incidentally, rms is a square root of a square average value.
It is difficult to provide a low jitter clock at the high frequency of 1 GS/s and sufficiently low power consumption. In other words, under present circumstances, it is difficult to provide an ultrafast and high-resolution analog-to-digital converter because of the jitter included in the sampling clock.
Patent Document 1 discloses a technique of digitally correcting the influence of a jitter at an output side of an analog-to-digital converter to reduce the deterioration of the effective resolution of the analog-to-digital converter caused by the jitter of the sampling clock. FIG. 1 shows an analog-to-digital converter adapting such a technique. The structure of the analog-to-digital converter 10 will be briefly explained below.
The analog-to-digital converter 10 includes a phase locked loop (PLL) 11, a divider 12, an analog-to-digital conversion unit 13, a time-to-digital converter (TDC) 14, and a digital correction unit 15.
The analog-to-digital converter 10 frequency-divides by divider 12 the output of the phase locked loop (PLL) 11 using an output from a crystal oscillator and the like as a source oscillation, and supplies a frequency-divided clock signal to the analog-to-digital conversion unit 13 as a sampling clock (ADC CLK). The analog-to-digital conversion unit 13 samples an input analog voltage using the sampling clock and executes the analog-to-digital conversion of the sampled voltage to output the converted voltage. However, the output value of the analog-to-digital conversion unit 13 is influenced by the jitter of the sampling clock.
Accordingly, the analog-to-digital converter 10 inputs the sampling clock and the output of the PLL 11 to the time-to-digital converter 14. The time difference (jitter value) between the sampling clock and the output of the PLL at each voltage transition timing is given to the digital correction unit 15 for correcting the influence of the jitter.
The time-to-digital converter 14 is intensely studied and developed in recent years. For example, Non-patent Document 5 discloses a time-to-digital converter having a time resolution of approximately 1 ps. The time-to-digital converter 14 detects a jitter value included in a sampling clock with reference to an output of the phase locked loop 11 that is a negligible low jitter.
The digital correction unit 15 estimates a sampling voltage error at each sampling timing from the time difference (jitter value) detected by the time-to-digital converter 14, and corrects a raw digital output of the analog-to-digital conversion unit 13 based on the estimation result. Consequently, the analog-to-digital converter 10 disclosed in Patent Document 1 eliminates the influence of the jitter included in the sampling clock from the raw digital output of the analog-to-digital conversion unit 13.    [Patent Document 1] US2008/80238752    [Patent Document 2] JP Patent Publication (Kokai) No. 2009-117894    [Non-patent Document 1] Takashi Oshima, Tomomi Takahashi, Taizo Yamawaki, Cheonguyen Tsang, Dusan Stepanovic and Borivoje Nikolic, “Fast nonlinear deterministic calibration of pipelined A/D converters,” 2008 51st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2008), pp. 914-917, August 2008.    [Non-patent Document 2] Takashi Oshima, Cheonguyen Tsang, Borivoje Nikolic, “Fast digital background calibration for pipelined A/D converters”, IEICE Technical Report, VLD2006-138, pp. 115-120, March 2007    [Non-patent Document 3] Takashi Oshima, Tomomi Takahashi and Taizo Yamawaki, “Novel sampling timing background calibration for time-interleaved A/D converters,” 2009 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2009), pp. 361-364, August 2009.    [Non-patent Document 4] Tomomi Takahashi and Takashi Oshima, “Highly accurate on-chip background calibration for time-interleaved A/D converters”, IEICE Transactions J93-A, pp. 613-625, September 2010.    [Non-patent Document 5] K. Nose, M. Kajita and M. Mizuno, “A 1-ps resolution jitter-measurement macro using interpolated jitter oversampling,” IEEE Journal of Solid-State Circuits, vol. 41, No. 12, pp. 2911-2920, December 2006.
In the circuit structure disclosed in Patent Document 1, attention is focused on the fact that the output of the phase locked loop 11 has a higher frequency and shorter cycle than the sampling clock of the analog-to-digital conversion unit 13. In other words, this circuit structure makes use of the fact that the jitter included in the output of the phase locked loop 11 is smaller than that of the sampling clock.
To operate the phase locked loop 11 to have a higher frequency than the sampling clock, however, large power consumption is required. For example, in Patent Document 1, the output of the phase locked loop is 8 GHz while the sampling clock is 250 MHz. The output of the phase locked loop has a remarkably higher frequency. This means that the output of the phase locked loop is 32 GHz, which is a high frequency, when the sampling clock is 1 GHz. The large power consumption and difficult high frequency circuit implementation are required. Thus, it is difficult to use the analog-to-digital converter disclosed in Patent Document 1 as an ultrafast and high-resolution analog-to-digital converter required for next-generation industrial altimeter measurement and wireless communication system.
As described above, the practical use of an analog-to-digital converter capable of digitally correcting the influence of a jitter included in a sampling clock at lower power consumption is desired.